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dc.contributor.authorCASTILLO ATOCHE, ALEJANDRO ARTURO
dc.contributor.authorVAZQUEZ CASTILLO, JAVIER
dc.date.accessioned2018-09-14T22:46:33Z
dc.date.available2018-09-14T22:46:33Z
dc.date.issued2012
dc.identifier.urihttp://hdl.handle.net/20.500.12249/1411
dc.description.abstractA high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a high-speed dual super-systolic array (SSA) core for the enhancement/reconstruction of remote sensing (RS) imaging of radar/synthetic aperture radar (SAR) sensor systems. The selected reconstructive SP algorithms are efficiently transformed in their parallel representation and then, they are mapped into an efficient high performance embedded computing (HPEC) architecture in reconfigurable Xilinx field programmable gate array (FPGA) platforms. As an implementation test case, the proposed approach was aggregated in a HW/SW co-design scheme in order to solve the nonlinear ill-posed inverse problem of nonparametric estimation of the power spatial spectrum pattern (SSP) from a remotely sensed scene. We show how such dual SSA core, drastically reduces the computational load of complex RS regularization techniques achieving the required real-time operational mode.
dc.description.provenanceSubmitted by Yaremi Isabel Can Chulin (1315421@uqroo.mx) on 2018-09-14T22:46:33Z No. of bitstreams: 1 Castillo-Atoche-A_A-new-tool-for-intelligent-parallel-processing-of-radarSAR-remotely-sensed-imageryOpen-Access_2013.pdf: 3924711 bytes, checksum: 8d63169516ad944f28f86de43a82c4d2 (MD5)
dc.description.provenanceMade available in DSpace on 2018-09-14T22:46:33Z (GMT). No. of bitstreams: 1 Castillo-Atoche-A_A-new-tool-for-intelligent-parallel-processing-of-radarSAR-remotely-sensed-imageryOpen-Access_2013.pdf: 3924711 bytes, checksum: 8d63169516ad944f28f86de43a82c4d2 (MD5) Previous issue date: 2012
dc.formatpdf
dc.language.isoeng
dc.publisherMDPI
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.sourceSensors
dc.subjectSuper-systolic
dc.subjectParallel computing
dc.subjectRemote sensing
dc.subjectFPGA
dc.subject.classificationINGENIERÍA Y TECNOLOGÍA
dc.titleDual super-systolic core for real-time reconstructive algorithms of high-resolution radar/SAR imaging systems.
dc.typeArtículo
dc.type.conacytarticle
dc.rights.accesopenAccess
dc.identificator7
dc.audiencegeneralPublic
dc.identifier.doi10.3390/s120302539
dc.divisionBiblioteca Unidad Académica Chetumal, Santiago Pacheco Cruz


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